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Cannot Use Generic Cmpxchg On Smp

So yes, architectures without native support (where "native" includes load-locked + store-conditional) always need to - on UP, just disable interrupts - on SMP, use a spinlock (with interrupts disabled), and It would be good (but perhaps not as strict a requirement) if the atomic counters also use the same lock. It is only protected against normalinterrupts, but this is enough for architectures without such interrupt sourcesor if used in a context where the data is not shared with such handlers.It can Linus From: Linus Torvalds Newsgroups: fa.linux.kernel Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch Date: Fri, 08 Dec 2006 19:39:17 UTC Message-ID: On Fri, 8 Dec have a peek here

All rights reserved. Toggle navigation Toggle navigation This project Loading... Russell - LL/SC simply isn't on the table as an interface, whether you like it or not. Yes. http://lxr.free-electrons.com/source/include/asm-generic/cmpxchg.h

I've never heard of anybody ever _architecturally_ saying that they support that strong requirements, even if certain micro- architectures might actually support stronger semantics than the ones guaranteed by the architectural Linus From: Linus Torvalds Newsgroups: fa.linux.kernel Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch Date: Fri, 08 Dec 2006 19:17:46 UTC Message-ID: On Fri, 8 Dec So what you easily end up with is (a) yes, you can actually get the compiler to generate the "obvious" code sequence 99% of the time, and it will all work

That does NOT mean that you can expose it widely as a portable interface - it's still just a very _nonportable_ interface that you use internally within one architecture to implement From: Linus Torvalds Newsgroups: fa.linux.kernel Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch Date: Wed, 06 Dec 2006 19:26:57 UTC Message-ID: On Wed, 6 Dec 2006, This works, but the more high-level it is, the more you end up having the same thing written in many different ways, and nasty maintenance. And Alpha could do that too.

It will allow lockless implementation for various performance > > criticial portions of the kernel. > > I suspect ARM may have been the last one without one, no? Index Home About Blog From: Linus Torvalds Newsgroups: fa.linux.kernel Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch Date: Wed, 06 Dec 2006 19:06:58 UTC Message-ID: On Sign in ARM / imx6_kernel_4.1 Go to a project Toggle navigation Toggle navigation pinning Projects Groups Snippets Help Project Activity Repository Pipelines Graphs Issues 0 Merge Requests 0 Wiki Network Create https://lkml.org/lkml/2007/8/20/222 Things like semaphore locking primitives are high-level enough already that we prefer to try to make them use common lower-level interfaces (spinlocks, cmpxchg etc).

You signed in with another tab or window. It seems specific to the or32 because most other platforms have an arch specific component that would have already included types.h ahead of time, but the o32 does not. Cc: Arnd Bergmann Cc: Jonas Does not * support SMP. */ #ifndef __ASM_GENERIC_CMPXCHG_H #define __ASM_GENERIC_CMPXCHG_H #ifdef CONFIG_SMP #error "Cannot use generic cmpxchg on SMP" #endif #include #include #ifndef xchg /* * This function doesn't The last one is the one that hits everybody, regardless of microarchitecture.

It doesn't make any sense from a microarchitectural standpoint (it's not how you'd normally implement these things), but it ALSO makes no sense from the way you already use those instructions Linus From: Linus Torvalds Newsgroups: fa.linux.kernel Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch Date: Wed, 06 Dec 2006 19:36:28 UTC Message-ID: On Wed, 6 Dec On alpha, the architecture manual says (I didn't go back and check, but I'm pretty sure) that a ld.l and st.c cannot have a taken branch in between then, for example. All of which means that _nobody_ can really do this reliably in C.

Which means that in a direct-mapped L1 cache, you can't even load anything that might be in the same way, because it would cause a cache eviction that invalidates the SC. Please register or login to post a comment I'm OK with using atomic_cmpxchg(); we have > atomic_set locked against it. If you write the C code a specific way, you can make it work.

It will allow lockless implementation for various performance > criticial portions of the kernel. That said, cmpxchg won't necessarily be "high-performance" unless the hw supports it naturally in hardware, so.. I could code atomic_add() as: Sure. http://homeshareware.com/cannot-use/cannot-use-the-generic-request-collection-after-calling-binaryread.html In other words, it's simply not an option to expose LL/SC as an interface.

Does not * support SMP. */ #ifndef __ASM_GENERIC_CMPXCHG_H #define __ASM_GENERIC_CMPXCHG_H Novell is a registered trademark and openSUSE and SUSE are trademarks of Novell, Inc.

Linus From: Linus Torvalds Newsgroups: fa.linux.kernel Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch Date: Fri, 08 Dec 2006 20:03:36 UTC Message-ID: On Fri, 8 Dec No. And like it or not, cmpxchg is the closest thing you can get to that. Does not 3 * support SMP. 4 */ 5 6 #ifndef __ASM_GENERIC_CMPXCHG_H 7 #define __ASM_GENERIC_CMPXCHG_H 8 9 #ifdef CONFIG_SMP 10 #error "Cannot use generic cmpxchg on SMP" 11 #endif 12 13

We recommend upgrading to the latest Safari, Google Chrome, or Firefox. Also, I don't see quite why you think "cmpxchg()" and "atomic_cmpxchg()" would be different. hosted at Digital OceanAdvertise on this siteĀ  cregit: contributors to the Linux kernel

Home Release 4.8 Release 4.7 Cregit version 1.0-rc1 cregit-Linux how code gets into the kernel Release 4.8 include/asm-generic/cmpxchg.h How do you to the atomic bitops?

Does not support SMP. */ #ifdef CONFIG_SMP #error "Cannot use generic cmpxchg on SMP" #endif /* * Atomic compare and exchange. * * Do not define __HAVE_ARCH_CMPXCHG because we want to So I don't think there's all that much more to be had there. Takes an u64 parameter.+ */+static inline u64 __cmpxchg64_local_generic(volatile void *ptr, u64 old, u64 new)+{+ u64 prev;+ unsigned long flags;++ local_irq_save(flags);+ if ((prev = *(u64*)ptr) == old)+ *(u64*)ptr = new;+ local_irq_restore(flags);+ return Linux Cross Reference Free Electrons Embedded Linux Experts •source navigation •diff markup •identifier search •freetext search • Version: 2.0.402.2.262.4.373.113.123.133.143.153.163.173.183.194.04.14.24.34.44.54.64.74.8 Linux/include/asm-generic/cmpxchg.h 1 /* 2 * Generic UP xchg and cmpxchg using interrupt

The ARM1136 manual explicitly states that any attempt to modify that address clears the tag (for shared memory regions, by _any_ CPU, and for nonshared regions by _that_ CPU). Really, Russell. Linus From: Al Viro Newsgroups: fa.linux.kernel Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch doesn't support it Date: Wed, 06 Dec 2006 19:09:03 UTC Message-ID: On So, you really do end up with three possibilities: - do things with TRULY PORTABLE interfaces.

We have a fairly big set of ops like "atomic_add_return()"-like operations, and those are the obvious ones that can be done for _any_ ll/sc architecture too. At some point you have to tell hardware designers that their hardware just sucks. - have ugly conditional code in generic code. I'm not sure. Russell, are you ok with the code DavidH posted (the "try 2" one)?

That basically means that you can't allow the compiler to reorder the basic blocks (which it often will with a while-loop). Linus From: Linus Torvalds Newsgroups: fa.linux.kernel Subject: Re: [PATCH] WorkStruct: Implement generic UP cmpxchg() where an arch Date: Fri, 08 Dec 2006 20:35:48 UTC Message-ID: On Fri, 8 Dec Well, you can on ARM at least. Linus Index Home About Blog Toggle navigation Toggle navigation This project Loading...

So I suspect you're wrong, and that the ldrex/strex tags actually are not all that different from other architectures which tend to have cacheline granularities or more (I _think_ the original Ie it might not be a matter of "within ten cycles", but "you need to randomize the timing").

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